1. Field of the Invention
The present invention relates to a synchronous semiconductor memory apparatus comprising a latch circuit for latching an output of an input circuit that receives input information.
In particular, the present invention relates to a synchronous semiconductor memory apparatus comprising a latch circuit capable of reducing current consumption and an input information latch control method thereof.
2. Description of Related Art
In recent years, in a semiconductor storage apparatus, with improvement in processing capability of a personal computer or the like, there has been a strong demand for high speed data access, and a synchronous semiconductor memory apparatus for data input/output in synchronism with an external clock has been significantly advanced and developed. At the same time, there has been remarkable improvement in technique for hand held device. In a semiconductor storage apparatus as well, lower current consumption is expected. In a typical product field, a hand held device having its high level computing capability such as mobile personal computer (PC) or notebook type personal computer (PC) has been significantly developed. As a semiconductor storage apparatus to be mounted on such device, a synchronous semiconductor memory apparatus are required which are capable of achieving an operation for low current compensation represented by a synchronous dynamic random access memory. Approaches for low current consumption includes a variety of measures described later, including control that has been achieved in a system inactive state such as power-down mode.
FIG. 1 is a circuit block diagram depicting an input buffer circuit that receives a signal from an external pin. A variety of control signals (Control) such as /CS,/RAS,/CAS,/WE or the like, bank address BankAdd or address Add, and data DQ or write mask signal DQM and the like are input to the external pin, and a level converter circuit (Level Converter) (refer to FIG. 15) detects whether a voltage level of an input signal is high or low comparing with a predetermined reference voltage Vrf. Then, this voltage level is converted into an amplification level of an internal circuit. This circuit is provided in a differential amplifier circuit system as shown in FIG. 15, and can be composed of a CMOS logic circuit or the like. The level converted input signal is level converted by means of a level converter circuit (Level Converter), and is latched by means of a latch circuit (Latch) (refer to FIG. 16) in synchronism with a rising edge of an internal synchronous clock (int. CLK) in which driving capability is improved by means of a driver circuit (Driver), thereby determining setup and hold specifications for a signal utilized for an internal circuit (Int. Circuit) and applied to an external pin.
Here, let us take an example of a 64 megabit synchronous semiconductor memory apparatus. A set of address Add is composed of 14 bits including 1 bit of bank address BankAdd, and a set of data DQ is composed of 32 DQs. With further high capacity and an increased number of DQs, the number of input buffer circuits represented by a set of address BankAdd, Add, and a set of data DQ is prone to increase.
FIG. 2 is a diagram showing operating waveforms. In synchronism with a rising edge of an internal synchronous signal int. CLK that is a signal in the same phase as a synchronous signal CLK, all latch circuits (Latch) performs latch operation, thereby performing a latch operation of the bank address BankAdd and row addresses in an active command (ACTV) cycle in FIG. 2. In FIG. 2, latch operation is performed in each cycle. In a current state in which a plenty of pins are provided, low current consumption in an input buffer circuit is an important factor, and a variety of measures are discussed and taken.
For example, in Japanese Laid-open Patent Publication No. 11-273341 that is the first prior art, in a clock synchronous semiconductor apparatus, as shown in FIG. 3, an input buffer 100 is composed of: a differential input buffer 101; a latch circuit 102 for latching a differential input buffer output; and a control circuit 103 for activating the differential input buffer 101 and the latch circuit 102 only at a predetermined timing.
That is, in the control circuit 103, when both of the power-down signal PD and latch signal QCLKB are inactive (low level), the differential input buffer 101 and the latch circuit 102 are activated. Then, a voltage level of an external input signal IN compared with a reference voltage Vref is differentially amplified at a differential input buffer 101, and is level converted as an output signal. Thereafter, a data holding operation is performed at the latch circuit 102. When at least one of the power-down signal PD and latch signal QCLKB is active (high level), an output NOR101 of the control circuit 103 turns OFF an NMOS transistor Q106. A signal obtained by inverting the output NOR101 by means of an inverter IV turns OFF a PMOS transistor Q105, and turns OFF a clocked inverter CIV that configures the latch circuit 102. Thus, a bias current of the differential input buffer 101 and a through current when data is switched in the latch circuit 102 do not flow altogether.
Therefore, in a normal operating state in which the power-down signal PD is inactive (low level), a latch signal QCLKB is inactive (low level) for a predetermined time in synchronism with a synchronous signal (clock) by which data is input, and is active (high level) in the subsequent latch period, whereby current consumption in an input data latch state is reduced.
In addition, in Japanese Laid-open Patent Publication No. 7-177015 that is the second prior art, in a synchronous semiconductor apparatus configuring two banks A and B, as shown in FIG. 4, when burst reading is performed in a bank selection state, the supply of a bias current to an input circuit at an initial stage is stopped.
That is, in the case where either one of the bank selection signals (signal ARAE for bank A and signal BRAE for bank B) enters a high level, and is selected (OR logic gate 201); a burst read signal READB enters a high level and a burst read state (OR logic gate 202); and a power-down signal PWDNB enters a low level, and is in a normal operating state, an output signal PWDNB2 obtained by inverting a logical product (NAND logic gate 203) of these signals (by an inverter 204) enters a high level. This output signal PWDNB2 is inverted by means of an inverter 205, and bias PMOS transistors 206 and 207 of an input circuit at an initial stage are turned OFF, thereby stopping the supply of a bias current to the input circuit at the initial stage.
In addition, the timing chart in the figure denotes a 4-bit burst read in bank A. Prior to cycle T1, when /RAS is set at a low level, and a bank A active command is recognized at a rising edge of a synchronous clock CLK at cycle T1, a bank A selection signal ARAE goes to a high level in cycle T1. Next, in cycle T1, /RAS goes to a high level, and /CAS goes to a low level. In cycle T2, a bank A read command is recognized. In cycle T2, a burst read signal READB goes to a low level. At this time, assuming that an output enable mask signal OEMSK maintains a low level, a signal PWDNB2 goes to a low level. In the subsequent cycle as well, a burst read operation is performed while a low level is maintained (T3 to T6).
Therefore, after a burst bank A selection signal ARAE goes to a high level in cycle T1, a signal PWDNB2 maintains a low level excluding a startup period of a burst read operation until the burst read signal READB goes to a low level in the subsequent cycle T2. Then, the power of an input circuit at the initial stage is cut in order to reduce current consumption.
Although a bank A burst read operation has been described above, of course, the similar operation is made for bank B.
In Japanese Laid-open Patent Publication No. 11-273341 that is the first prior art, the activation period of the input buffer 100 is limited to a predetermined time from a falling edge of a synchronous clock. However, in order to enable operation in all the clock cycles, as shown in FIG. 2, in the case where a potential state of an external pin is unstable instead of a cycle of inputting addresses or data and the like (DSEL, NOP in FIG. 2) as well, a command acquisition operation is performed. Thus, there is a problem that there flow currents such as a bias current of an unnecessary differential input buffer 101, a through current during inversion data latching in the latch circuit 102, and further, a charging/discharging current of an internal signal line during data inversion, and current consumption cannot be reduced.
Here, a cycle in which a command or the like is not input denotes a wait cycle (NOP cycle) in which, for example, in the case where an active command is accepted, a read operation cannot be performed for a time in which data is read out from a memory cell as an internal operation, and amplified by means of a sensing amplifier, and thus, in the case where a synchronous clock frequency is particularly at a high speed, data can be read out from an active command to a read command. In this non-operation (NOP) cycle, data stored in a memory cell is amplified by means of a sensing amplifier. Although a command or the like from an external pin cannot be accepted, a synchronous clock is input to an input buffer 100. Thus, since input signal level conversion and latch operation are performed, wasteful current consumption is generated, and current consumption cannot be reduced, which is problematic.
Further, a bank A pre-charge command is accepted at the end of a burst read operation. However, in this case, a required address is only a bank address for specifying a bank. Although a normal address is unnecessary, all the input buffers 100 for inputting addresses are activated. Thus, with respect to such unnecessary addresses, level conversion and latch operation are performed. Thus, wasteful current consumption is generated, and current consumption cannot be reduced, which is problematic.
An input buffer 100 in which the supply of a bias current is stopped at the end of a clock cycle, and operation is stopped, must start the supply of a bias current at the rising edge or falling edge of a synchronous clock in the next cycle, and acquire a command or the like. In a current state in which specifications for setup and hold times of commands or the like are severe with high speed operation, the supply of the bias current and command acquisition prevent high speed operation, which is problematic.
In addition, in Japanese Laid-open Patent Publication No. 7-177015 that is the second prior art, a bias current is supplied to an input current at the initial stage by means of bank selection signals ARAE and BRAE activated based on a command for accepting at the rising edge of the synchronous clock. The number of logic gate stages from the rising edge of the synchronous clock to activation of the bank selection signals ARAE and BRAE requires some ten stages. Thus, there is a problem that its propagation delay cannot conform to specifications for setup and hold times of an input signal, and the activation of an input circuit at the initial stage for inputting data or address and the like is delayed in accordance with a cycle of a synchronous clock for activating the input circuit at the initial stage. Therefore, the prior art is limited to application to the input circuit at the initial stage which does not require signal acquisition at the same cycle as bank activation command, and is limited to reduction of current consumption, which is problematic.
In addition, in the timing chart shown in FIG. 4, although the cycle of a bank A active command and a cycle of a read command are adjacent, a semiconductor storage apparatus receiving a bank A active command reads out data from the memory cell and performs amplifying operation at the sensing amplifier, making it necessary to be ready for a read command at the next step. In the case where an amplifying operation at the sensing amplifier can be executed at one synchronous clock cycle from data readout from the memory cell, a read command can be executed from the bank A active command at a continuous clock cycle, as shown in the timing chart of FIG. 4. However, in a current state in which speeding up synchronous clock is advanced with high speed operation in recent years, a time required for internal amplifying operation requires synchronous clock cycle or more, thus making it necessary to insert a non-operation (NOP) cycle until the read command is obtained. The required number of non-operation (NOP) cycles is prone to increase with higher synchronous clock cycle. In the prior art shown in FIG. 4, during this non-operation (NOP) cycle period, an input circuit at the initial stage is activated. Thus, unnecessary operation of the input circuit at the initial stage increases with advancement for high speed operation, and current consumption cannot be reduced, which is problematic.
The present invention has been made in order to solve the foregoing problem. It is an object of the present invention to provide a synchronous semiconductor memory apparatus in which an input buffer circuit is activated only at a required operating cycle without degrading input buffer high speed response properties, whereby unnecessary current consumption can be reduced, and low current consumption can be achieved while high speed response properties relevant to an input signal is maintained.
In order to achieve the foregoing object, according to one aspect of the present invention, there is provided a synchronous semiconductor memory apparatus, comprising: a first input circuit receiving a synchronous signal; one or more second input circuits receiving a control signal; and third input circuits for an access to individual memory cells; and first latch circuits for latching output signals of the third input circuits according to an output signal of a logic circuit receiving an output signal from the first input circuit and one or more second input circuits.
In addition, according to one aspect of the present invention, there is provided a method for latching and controlling input information on a synchronous semiconductor memory apparatus, comprising the steps of: inputting a synchronous signal, one or more control signals, and information required for access to individual memory cells; the synchronous signal input step; and the first latch step of latching output signals obtained from the information input step according to an output signal obtained from the logic step of inputting an output signal obtained from the control signal input step.
In the synchronous semiconductor memory apparatus and a method for latching and controlling input information on the synchronous semiconductor memory apparatus, information required for memory access is latched according to the output result logically computed based on a logic relationship between the synchronous signal and one or more control signals.
In this manner, in the case where an output signal of the third input circuit for inputting input information such as address or data or the like required for access to a memory cell is latched by means of the first latch circuit only according to a logical relationship obtained as an output signal of a logic circuit for inputting a synchronous signal that is an output signal of the first input circuit and one or more control signals input to the second input circuit, and in the case where a logic circuit does not output an output signal because a control signal does not coincide with a predetermined logical relationship, no latch operation is performed. This, a latch operation can be performed only in the case where there exists a signal to be input to an input terminal of the third input circuit. When a signal level is unstable, latch data inversion due to unnecessary latch operation caused by a synchronous signal does not occur. In a normal operating state, latch operation can be dynamically performed for each operating cycle, and there does not occur current consumption of a through current or the like of a latch circuit caused by data inversion due to unnecessary latch operation or current consumption caused by charge and discharge operations of an output signal line in a latch circuit.
In addition, a latch circuit is controlled by means of an output signal of a logic circuit instead of the synchronous signal. Thus, a load on a signal line connected to an output signal of the first input circuit can be reduced, and current consumption when the synchronous signal is driven can be reduced.
Further, low current consumption can be accelerated while an active state is maintained without performing control for activation of the first to third input circuits, and thus, low current consumption can be achieved without preventing high speed response properties relevant to an input signal.
The above and further objects and novel features of the invention will more fully appear from following detailed description when the same is read in connection with the accompanying drawings. It is to be expressly understood, however, that the drawings are purpose of illustration only and not intended as a definition of the limits of the invention.